View OP46707_4139718.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Quad Precision, High Speed Operational Amplifier OP467
FEATURES
High slew rate: 170 V/s Wide bandwidth: 28 MHz Fast settling time: <200 ns to 0.01% Low offset voltage: <500 V Unity-gain stable Low voltage operation: 5 V to 15 V Low supply current: <10 mA Drives capacitive loads
PIN CONFIGURATIONS
OUT A 1 -IN A 2 +IN A 3 V+ 4 +IN B 5 -IN B 6 OUT B 7
+ + + + 14 OUT D 13 -IN D 12 +IN D
OP467
11 V- 10 +IN C 9 8
-IN C OUT C
00302-001
Figure 1. 14-Lead CERDIP (Y Suffix) and 14-Lead PDIP (P Suffix)
OUT A OUT D -IN A NC
1
+IN B 5 -IN B 6 OUT B 7 NC
8
12 +IN C 11 -IN C
00302-002
OUT C
NC
The OP467 is a quad, high speed, precision operational amplifier. It offers the performance of a high speed op amp combined with the advantages of a precision op amp in a single package. The OP467 is an ideal choice for applications where, traditionally, more than one op amp was used to achieve this level of speed and precision. The internal compensation of the OP467 ensures stable unitygain operation, and it can drive large capacitive loads without oscillation. With a gain bandwidth product of 28 MHz driving a 30 pF load, output slew rate is 170 V/s, and settling time to 0.01% in less than 200 ns, the OP467 provides excellent dynamic accuracy in high speed data acquisition systems. The channel-to-channel separation is typically 60 dB at 10 MHz. The dc performance of the OP467 includes less than 0.5 mV of offset, a voltage noise density below 6 nV/Hz, and a total supply current under 10 mA. The common-mode rejection ratio (CMRR) is typically 85 dB. The power supply rejection ratio (PSRR) is typically 107 dB. PSRR is maintained to better than 40 dB with input frequencies as high as 1 MHz. The low offset and drift plus high speed and low noise make the OP467 usable in applications such as high speed detectors and instrumentation. The OP467 is specified for operation from 5 V to 15 V over the extended industrial temperature range (-40C to +85C) and is available in a 14-lead PDIP, a 14-lead CERDIP, a 16-lead SOIC, and a 20-terminal LCC. Contact your local sales office for the MIL-STD-883 data sheet and availability.
Rev. F
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
9
NC
NC = NO CONNECT
NC = NO CONNECT
Figure 2. 16-Lead SOIC (S Suffix)
Figure 3. 20-Terminal LCC (RC Suffix)
OUT B
-IN B
-IN C
GENERAL DESCRIPTION
10 OUT C
9
10 11 12 13
V+
+IN -IN
OUT
V-
Figure 4. Simplified Schematic
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2007 Analog Devices, Inc. All rights reserved.
00302-004
00302-003
High speed image display drivers High frequency active filters Fast instrumentation amplifiers High speed detectors Integrators Photo diode preamps
3
2
20 19 18
-IN D
APPLICATIONS
+IN A 4 NC 5 V+ 6 NC 7 +IN B 8
OUT A 1 -IN A 2 +IN A 3 V+ 4
16 OUT D 15 -IN D 14 +IN D
+IN D NC V- NC +IN C
OP467
(TOP VIEW)
17 16 15 14
OP467
13 V-
OP467 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Pin Configurations ........................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Electrical Characteristics............................................................. 3 Wafer Test Limits.......................................................................... 5 Absolute Maximum Ratings............................................................ 6 Thermal Resistance ...................................................................... 6 Dice Characteristics ..................................................................... 6 ESD Caution.................................................................................. 6 Typical Performance Characteristics ............................................. 7 Applications Information .............................................................. 13 Output Short-Circuit Performance.......................................... 13 Unused Amplifiers ..................................................................... 13 Printed Circuit Board (PCB) Layout Considerations ........... 13 Grounding ................................................................................... 13 Power Supply Considerations................................................... 13 Signal Considerations ................................................................ 13 Phase Reversal ............................................................................ 14 Saturation Recovery Time......................................................... 14 High Speed Instrumentation Amplifier .................................. 14 2 MHz Biquad Band-Pass Filter ............................................... 15 Fast I-to-V Converter ................................................................ 16 OP467 SPICE Marco-Model..................................................... 17 Outline Dimensions ....................................................................... 19 Ordering Guide .......................................................................... 20
REVISION HISTORY
5/07--Rev. E to Rev. F Updated Format..................................................................Universal Changes to General Description .................................................... 1 Changes to Table 1............................................................................ 3 Changes to Table 2............................................................................ 4 Changes to Table 3............................................................................ 5 Updated Outline Dimensions ....................................................... 19 Changes to Ordering Guide .......................................................... 20 3/04--Rev. D to Rev. E Changes to TPC 1 ............................................................................. 5 Changes to Ordering Guide ............................................................ 4 Updated Outline Dimensions ....................................................... 16 4/01--Rev. C to Rev. D Footnote added to Power Supply.....................................................2 Footnote added to Max Ratings ......................................................4 Edits to Power Supply Considerations Section........................... 11
Rev. F | Page 2 of 20
OP467 SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
@ VS = 15.0 V, TA = 25C, unless otherwise noted. Table 1.
Parameter INPUT CHARACTERISTICS Offset Voltage Input Bias Current Input Offset Current Common-Mode Rejection Large Signal Voltage Gain Offset Voltage Drift Bias Current Drift Long-Term Offset Voltage Drift 1 OUTPUT CHARACTERISTICS Output Voltage Swing POWER SUPPLY 2 Power Supply Rejection Ratio Supply Current Supply Voltage Range DYNAMIC PERFORMANCE Gain Bandwidth Product Slew Rate GBP SR AV = +1, CL = 30 pF VIN = 10 V step, RL = 2 k, CL = 30 pF AV = +1 AV = -1 VIN = 10 V step To 0.01%, VIN = 10 V step 28 125 170 350 2.7 200 45 2.0 1.0 eN p-p eN iN f = 0.1 Hz to 10 Hz f = 1 kHz f = 1 kHz 0.15 6 0.8 MHz V/s V/s MHz ns Degrees pF pF V p-p nV/Hz pA/Hz Symbol VOS IB IOS CMR CMR AVO VOS/T IB/T VOS/T VO RL = 2 k RL = 2 k, -40C TA +85C 4.5 V VS 18 V -40C TA +85C VO = 0 V VO = 0 V, -40C TA +85C 13.0 12.9 96 86 -40C TA +85C VCM = 0 V VCM = 0 V, -40C TA +85C VCM = 0 V VCM = 0 V, -40C TA +85C VCM = 12 V VCM = 12 V, -40C TA +85C RL = 2 k RL = 2 k, -40C TA +85C Conditions Min Typ 0.2 150 150 10 10 90 88 86 3.5 0.2 750 13.5 13.12 120 115 8 Max 0.5 1 600 700 100 150 Unit mV mV nA nA nA nA dB dB dB dB V/C pA/C V V V dB dB mA mA V
80 80 83 77.5
PSRR ISY VS
4.5
10 13 18
Full-Power Bandwidth Settling Time Phase Margin Input Capacitance Common Mode Differential NOISE PERFORMANCE Voltage Noise Voltage Noise Density Current Noise Density
1 2
BW tS 0
Long-term offset voltage drift is guaranteed by 1000 hrs. Life test performed on three independent wafer lots at 125C, with an LTPD of 1.3. For proper operation, the positive supply must be sequenced ON before the negative supply.
Rev. F | Page 3 of 20
OP467
@ VS = 5.0 V, TA = 25C, unless otherwise noted. Table 2.
Parameter INPUT CHARACTERISTICS Offset Voltage Input Bias Current Input Offset Current Common-Mode Rejection Large Signal Voltage Gain Offset Voltage Drift Bias Current Drift OUTPUT CHARACTERISTICS Output Voltage Swing POWER SUPPLY Power Supply Rejection Ratio Supply Current DYNAMIC PERFORMANCE Gain Bandwidth Product Slew Rate Symbol VOS IB IOS CMR CMR AVO VOS/T IB/T VO RL = 2 k RL = 2 k, -40C TA +85C 4.5 V VS 5.5 V -40C TA +85C VO = 0 V VO = 0 V, -40C TA +85C AV = +1 VIN = 5 V step, RL = 2 k, CL = 39 pF AV = +1 AV = -1 VIN = 5 V step To 0.01%, VIN = 5 V step 3.0 3.0 92 83 -40C TA +85C VCM = 0 V VCM = 0 V, -40C TA +85C VCM = 0 V VCM = 0 V, -40C TA +85C VCM = 2.0 V VCM = 2.0 V, -40C TA +85C RL = 2 k RL = 2 k, -40C TA +85C Conditions Min Typ 0.3 125 150 20 76 76 80 74 85 80 83 3.5 0.2 3.5 3.20 107 105 8 Max 0.5 1 600 700 100 150 Unit mV mV nA nA nA nA dB dB dB dB V/C pA/C V V dB dB mA mA MHz V/s V/s MHz ns Degrees V p-p nV/Hz pA/Hz
PSRR ISY
10 12
GBP SR
22 90 90 2.5 280 45 0.15 7 0.8
Full-Power Bandwidth Settling Time Phase Margin NOISE PERFORMANCE Voltage Noise Voltage Noise Density Current Noise Density
BW tS 0 eN p-p eN iN
f = 0.1 Hz to 10 Hz f = 1 kHz f = 1 kHz
Rev. F | Page 4 of 20
OP467
WAFER TEST LIMITS 1
@ VS = 15.0 V, TA = 25C, unless otherwise noted. Table 3.
Parameter Offset Voltage Input Bias Current Input Offset Current Input Voltage Range 2 Common-Mode Rejection Ratio Power Supply Rejection Ratio Large Signal Voltage Gain Output Voltage Range Supply Current
1
Symbol VOS IB IOS CMRR PSRR AVO VO ISY
Conditions VCM = 0 V VCM = 0 V VCM = 12 V V = 4.5 V to 18 V RL = 2 k RL = 2 k VO = 0 V, RL =
Limit 0.5 600 100 12 80 96 83 13.0 10
Unit mV max nA max nA max V min/max dB min dB min dB min V min mA max
Electrical tests and wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard product dice. Consult sales to negotiate specifications based on dice lot qualifications through sample lot assembly and testing. 2 Guaranteed by CMR test.
Rev. F | Page 5 of 20
OP467 ABSOLUTE MAXIMUM RATINGS
Table 4.
Parameter 1 Supply Voltage 2 Input Voltage 3 Differential Input Voltage3 Output Short-Circuit Duration Storage Temperature Range 14-Lead CERDIP and 20-Terminal LCC 14-Lead PDIP and 16-Lead SOIC Operating Temperature Range OP467A OP467G Junction Temperature Range 14-Lead CERDIP and 20-Terminal LCC 14-Lead PDIP and 16-Lead SOIC Lead Temperature (Soldering, 60 sec)
1
Rating 18 V 18 V 26 V Limited -65C to +175C -65C to +150C -55C to +125C -40C to +85C -65C to +175C -65C to +150C 300C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
THERMAL RESISTANCE
JA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 5.
Package Type 14-Lead CERDIP (Y) 14-Lead PDIP (P) 16-Lead SOIC (S) 20-Terminal LCC (RC)
1
Absolute maximum ratings apply to both DICE and packaged parts, unless otherwise noted. 2 For proper operation, the positive supply must be sequenced ON before the negative supply. 3 For supply voltages less than 18 V, the absolute maximum input voltage is equal to the supply voltage.
JA1 94 76 88 78
JC 10 33 23 33
Unit C/W C/W C/W C/W
JA is specified for the worst-case conditions, that is, JA is specified for device in socket for CERDIP, PDIP, and LCC packages, and JA is specified for device soldered in circuit board for the SOIC package.
DICE CHARACTERISTICS
OUT A
2 1 -IN A 14
OUT D
13 -IN D
+IN A 3
12 +IN D
V+
4 11 V-
+IN B 5
10 +IN C
-IN B
6
7
8
9
-IN C
OUT B
Figure 5. 0.111 Inch x 0.100 Inch DIE Size, 11,100 sq. mils, Substrate Connected to V+, 165 Transistors
ESD CAUTION
Rev. F | Page 6 of 20
OUT C
00302-005
OP467 TYPICAL PERFORMANCE CHARACTERISTICS
80 70 60 VS = 15V RL = 1M CL = 30pF
100 VS = 15V TA = 25C 80
PHASE SHIFT (Degrees)
OPEN-LOOP GAIN (dB)
GAIN
IMPEDANCE ()
50 40 30 20 10 0 -10 -20 1k
AVCL = +100 60
PHASE
-90 -135 -180
40 AVCL = +10 20
00302-006
AVCL = +1 0 100 1k 10k FREQUENCY (Hz) 100k 1M
10k
100k
1M
10M
100M
FREQUENCY (Hz)
Figure 6. Open-Loop Gain, Phase vs. Frequency
80 VS = 15V TA = 25C 60
CLOSED-LOOP GAIN (dB)
Figure 9. Closed-Loop Output Impedance vs. Frequency
0.3 0.2 VS = 5V
GAIN ERROR (dB)
40
0.1 0.0 -0.1 -0.2 -0.3 VS = 15V
20
0
00302-007
-20 10k
100k
1M FREQUENCY (Hz)
10M
100M
0 100k
1M FREQUENCY (Hz)
3.4
5.8
10M
Figure 7. Closed-Loop Gain vs. Frequency
25
30
Figure 10. Gain Error vs. Frequency
AVCL = -1
OPEN-LOOP GAIN (V/mV)
TA = +125C 15
MAXIMUM OUTPUT SWING (V)
20
25 AVCL = +1 20
15
10
TA = +25C TA = -55C
10 VS = 15V TA = 25C RL = 2k 10k 100k FREQUENCY (Hz) 1M
5
00302-008
5
0 0 5 10 SUPPLY VOLTAGE (V) 15 20
0 1k
10M
Figure 8. Open-Loop Gain vs. Supply Voltage
Figure 11. Maximum VOUT Swing vs. Frequency
Rev. F | Page 7 of 20
00302-011
00302-010
00302-009
OP467
12 VS = 5V TA = 25C RL = 2k 60 VS = 15V RL = 2k VVIN = 100mV p-p AVCL = +1 AVCL = -1
10
MAXIMUM OUTPUT SWING (V)
AVCL = +1
50
AVCL = -1 6
OVERSHOOT (%)
00302-012
8
40
30
4
20
2
10
00302-015
0 1k
0 0 200 400 600 800 1000 1200 1400 LOAD CAPACITANCE (pF)
10k
100k FREQUENCY (Hz)
1M
10M
1600
Figure 12. Maximum VOUT Swing vs. Frequency
120 VS = 15V TA = 25C
Figure 15. Small Signal Overshoot vs. Load Capacitance
60 VS = 15V RL = 2k VVIN = 100mV p-p AVCL = +1 AVCL = -1
COMMON-MODE REJECTION (V)
100
50
60
OVERSHOOT (%)
00302-013
80
40
30
40
20
20
10
00302-016
0 1k
0 0 200 400 600 800 1000 1200 1400 LOAD CAPACITANCE (pF)
10k
100k FREQUENCY (Hz)
1M
10M
1600
Figure 13. Common-Mode Rejection vs. Frequency
120 VS = 15V TA = 25C
Figure 16. Small Signal Overshoot vs. Load Capacitance
60 50 40 30 1000pF 10000pF VS = 15V
POWER SUPPLY REJECTION (dB)
100
80
GAIN (dB)
20 10 0 -10 -20 CIN = NETWORK ANALYZER
500pF 200pF
60
40
20
00302-014
-30 -40 10k
0 100
1k
10k FREQUENCY (Hz)
100k
1M
100k
1M FREQUENCY (Hz)
10M
100M
Figure 14. Power-Supply Rejection vs. Frequency
Figure 17. Noninverting Gain vs. Capacitive Loads
Rev. F | Page 8 of 20
00302-017
OP467
0 VS = 15V -10
4 3 2
VOUT ERROR (mV)
CHANNEL SEPARATION (dB)
-20 -30 -40 -50 -60 -70 -80 -90 -100 100
00302-018
VS = 15V VIN = 5V CL = 50pF
1 0 -1 -2
00302-021
-3 -4 0 100 200 300 400 500 TIME (ns)
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
Figure 18. Channel Separation vs. Frequency
12
INPUT CURRENT NOISE DENSITY (pA/Hz)
Figure 21. Settling Time, Negative Edge
4
5V VS 15V 10
3 2
VOUT ERROR (mV)
VS = 15V VIN = 5V CL = 50pF
8
1 0 -1 -2
6
4
2
00302-019
0 1 10 100 FREQUENCY (Hz) 1k
-4 0 100 200 300 400 500 TIME (ns)
Figure 19. Input Current Noise Density vs. Frequency
Figure 22. Settling Time, Positive Edge
100
20 15
INPUT VOLTAGE RANGE (V)
TA = 25C
VOLTAGE NOISE DENSITY (nV/Hz)
10 5 0 -5 -10
00302-023
10
00302-020
-15 -20 0 5 10 SUPPLY VOLTAGE (V) 15 20
1.0 0.1
1
10
100
1k
10k
FREQUENCY (Hz)
Figure 20. Voltage Noise Density vs. Frequency
Figure 23. Input Voltage Range vs. Supply Voltage
Rev. F | Page 9 of 20
00302-022
-3
OP467
50 40 30 20
GAIN (dB)
500
VS1 = 15V VS2 = 5V RL = 10k CL = 50pF VS1 = 15V
UNITS
VS = 15V TA = 25C 1252 x OP AMPS 400
10 0 -10 -20 -30 -40 -50 10k
300
200
VS2 = 5V
100
00302-024
100k
1M FREQUENCY (Hz)
10M
100M
0 -100
-50
0
50
100
150
200
250
300
350
400
INPUT OFFSET VOLTAGE (VOS V)
Figure 24. Noninverting Gain vs. Supply Voltage
Figure 27. Input Offset Voltage Distribution
14 12 10 8 6
500
VS = 15V TA = 25C
400
VS = 5V TA = 25C 1252 x OP AMPS
OUTPUT SWING (V)
POSITIVE SWING
UNITS
300
NEGATIVE SWING 4
200
100
00302-025 00302-028
2 0 10
100
1k
10k
0 -100
-50
0
50
100
150
200
250
300
350
400
LOAD RESISTANCE ()
INPUT OFFSET VOLTAGE (VOS V)
Figure 25. Output Swing vs. Load Resistance
5
500
Figure 28. Input Offset Voltage Distribution
VS = 15V TA = 25C
400
VS = 15V TA = 25C 1252 x OP AMPS
4 OUTPUT SWING (V) POSITIVE SWING 3 NEGATIVE SWING UNITS
300
2
200
1
00302-026
100
00302-029
0 10
0
100
1k
10k
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
LOAD RESISTANCE ()
TC VOS (V/C)
Figure 26. Output Swing vs. Load Resistance
Figure 29. TC VOS Distribution
Rev. F | Page 10 of 20
00302-027
OP467
500 VS = 5V TA = 25C 1252 x OP AMPS 400
400 350 300 VS = 5V RL = 2k AVCL = +1
SLEW RATE (V/s)
300
250 200 +SR 150 100
UNITS
200
100
00302-030
-SR
00302-033
50 0 -75
0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
-50
-25
0
25
50
75
100
125
TC VOS (V/C)
TEMPERATURE (C)
Figure 30. TC VOS Distribution
Figure 33. Slew Rate vs. Temperature
60 GBW
29.0
650 600 550 VS = 15V RL = 2k AVCL = -1
GAIN BANDWIDTH PRODUCT (MHz)
PHASE MARGIN (Degrees)
55 VS = 5V RL = 2k 50 M 45
28.5
-SR
SLEW RATE (V/s)
500 +SR 450 400 350
28.0
27.5
00302-031
40 -75
-50
-25
0
25
50
75
100
27.0 125
250 -75
-50
-25
0
25
50
75
100
125
TEMPERATURE (C)
TEMPERATURE (C)
Figure 31. Phase Margin and Gain Bandwidth vs. Temperature
400 350 300 VS = 5V RL = 2k AVCL = -1 400 350 300
Figure 34. Slew Rate vs. Temperature
VS = 15V RL = 2k AVCL = +1
SLEW RATE (V/s )
250 200
SLEW RATE (V/s)
+SR 250 200 -SR 150 100
-SR
+SR 150 100
00302-032
0 -75
-50
-25
0
25
50
75
100
125
0 -75
-50
-25
0
25
50
75
100
125
TEMPERATURE (C)
TEMPERATURE (C)
Figure 32. Slew Rate vs. Temperature
Figure 35. Slew Rate vs. Temperature
Rev. F | Page 11 of 20
00302-035
50
50
00302-034
300
OP467
10 8 RF = 5k TA = 25C 5 4
200 VS = 15V
OUTPUT STEP FOR 5V SUPPLY (V)
OUTPUT STEP FOR 15V SUPPLY (V)
6 4 2 0 -2 -4 -6 -8 -10 0 100 0.1% 0.1%
0.1%
3 2 1 0 -5 0.1% -4 -3 -2 200 SETTLING TIME (ns) 300 -1 400
160
INPUT BIAS CURRENT (nA)
00302-036
120
90
40
00302-038
0 -75
-50
-25
0
25
50
75
100
125
TEMPERATURE (C)
Figure 36. Output Step vs. Settling Time
25 10
INPUT OFFSET CURRENT (nA)
Figure 38. Input Bias Current vs. Temperature
VS = 15V TA = +125C 20
8
SUPPLY CURRENT (mA)
TA = +25C 6
15
TA = -55C
10
4
5
00302-039
2
00302-037
0 -75
-50
-25
0
25
50
75
100
125
0
0
5
10 SUPPLY VOLTAGE (V)
15
20
TEMPERATURE (C)
Figure 37. Supply Current vs. Supply Voltage
Figure 39. Input Offset Current vs. Temperature
Rev. F | Page 12 of 20
OP467 APPLICATIONS INFORMATION
OUTPUT SHORT-CIRCUIT PERFORMANCE
To achieve a wide bandwidth and high slew rate, the OP467 output is not short-circuit protected. Shorting the output to ground or to the supplies may destroy the device. For safe operation, the output load current should be limited so that the junction temperature does not exceed the absolute maximum junction temperature. The maximum internal power dissipation can be calculated by A practical solution to this problem is to reduce the resonance frequency low enough to take advantage of the power supply rejection of the amplifier. This is easily done by placing capacitors across the supply line and the ground plane as close as possible to the device pin. Because capacitors also have internal parasitic components, such as stray inductance, selecting the right capacitor is important. To be effective, they should have low impedance over the frequency range of interest. Tantalum capacitors are an excellent choice for their high capacitance/size ratio, but their effective series resistance (ESR) increases with frequency making them less effective. On the other hand, ceramic chip capacitors have excellent ESR and effective series inductance (ESL) performance at higher frequencies, and because of their small size, they can be placed very close to the device pin, further reducing the stray inductance. Best results are achieved by using a combination of these two capacitors. A 5 F to 10 F tantalum parallel capacitor with a 0.1 F ceramic chip capacitor is recommended. If additional isolation from high frequency resonances of the power supply is needed, a ferrite bead should be placed in series with the supply lines between the bypass capacitors and the power supply. Note that addition of the ferrite bead introduces a new pole and zero to the frequency response of the circuit and could cause unstable operation if it is not selected properly.
+VS + 10F TANTALUM 0.1F CERAMIC CHIP
PD =
TJ max - TA JA
where: TJ and TA are junction and ambient temperatures, respectively. PD is device internal power dissipation. JA is the packaged device thermal resistance given in the data sheet.
UNUSED AMPLIFIERS
It is recommended that any unused amplifiers in the quad package be connected as a unity-gain follower with a 1 k feedback resistor with noninverting input tied to the ground plain.
PRINTED CIRCUIT BOARD (PCB) LAYOUT CONSIDERATIONS
Satisfactory performance of a high speed op amp largely depends on a good PCB layout. To achieve the best dynamic performance, follow the high frequency layout technique.
GROUNDING
A good ground plain is essential to achieve the optimum performance in high speed applications. It can significantly reduce the undesirable effects of ground loops and IR drops by providing a low impedance reference point. Best results are obtained with a multilayer board design with one layer assigned to the ground plain. To maintain a continuous and low impedance ground, avoid running any traces on this layer.
0.1F CERAMIC CHIP
00302-040
10F TANTALUM -VS
Figure 40. Recommended Power Supply Bypass
POWER SUPPLY CONSIDERATIONS
For proper operation, the positive supply must be sequenced on before the negative supply. All users should take steps to ensure this. In high frequency circuits, device lead length introduces an inductance in series with the circuit. This inductance, combined with stray capacitance, forms a high frequency resonance circuit. Poles generated by these circuits cause gain peaking and additional phase shift, reducing the phase margin of the op amp and leading to an unstable operation.
SIGNAL CONSIDERATIONS
Input and output traces need special attention to assure a minimum stray capacitance. Input nodes are very sensitive to capacitive reactance, particularly when connected to a high impedance circuit. Stray capacitance can inject undesirable signals from a noisy line into a high impedance input. Protect high impedance input traces by providing guard traces around them, which also improves the channel separation significantly. Additionally, any stray capacitance in parallel with the input capacitance of the op amp generates a pole in the frequency response of the circuit. The additional phase shift caused by this pole reduces the gain margin of the circuit. If this pole is within the gain range of the op amp, it causes unstable performance. To reduce these undesirable effects, use the lowest impedance where possible. Lowering the impedance at this node places the poles at a higher frequency, far above the gain range of the
Rev. F | Page 13 of 20
OP467
amplifier. Stray capacitance on the PCB can be reduced by making the traces narrow and as short as possible. Further reduction can be realized by choosing a smaller pad size, increasing the spacing between the traces, and using PCB material with a low dielectric constant insulator (dielectric constant of some common insulators: air = 1, Teflon(R) = 2.2, and FR4 = 4.7, with air being an ideal insulator). Removing segments of the ground plane directly under the input and output pads is recommended. Outputs of high speed amplifiers are very sensitive to capacitive loads. A capacitive load introduces a pair of pole and zero to the frequency response of the circuit, reducing the phase margin, leading to unstable operation or oscillation. Generally, it is good design practice to isolate the output of the amplifier from any capacitive load by placing a resistor between the output of the amplifier and the rest of the circuits. A series resistor of 10 to 100 is normally sufficient to isolate the output from a capacitive load. The OP467 is internally compensated to provide stable operation and is capable of driving large capacitive loads without oscillation. Sockets are not recommended because they increase the lead inductance/capacitance and reduce the power dissipation of the package by increasing the thermal resistance of the leads. If sockets must be used, use Teflon or pin sockets with the shortest possible leads.
10 0%
DLY 9.824s
100 90
10 0%
5V
5V
20ns
Figure 42. Saturation Recovery Time, Positive Rail
DLY 4.806s
100 90
5V
5V
20ns
Figure 43. Saturation Recovery Time, Negative Rail
PHASE REVERSAL
The OP467 is immune to phase reversal; its inputs can exceed the supply rails by a diode drop without any phase reversal.
V1
100
HIGH SPEED INSTRUMENTATION AMPLIFIER
The OP467 performance lends itself to a variety of high speed applications, including high speed precision instrumentation amplifiers. Figure 44 represents a circuit commonly used for data acquisition, CCD imaging, and other high speed applications. The circuit gain is set by RG. A 2 k resistor sets the circuit gain to 2; for unity gain, remove RG. For any other gain settings, use the following formula G = 2/RG (Resistor Value is in k) RC is used for adjusting the dc common-mode rejection, and CC is used for ac common-mode rejection adjustments.
-VIN
15.8V
OUTPUT 90
10
INTPUT 0% 10V 10V 200s
00302-041
CC
Figure 41. No Phase Reversal (AV = +1)
2k 1k RG 10k 1k 1.9k 10k +VIN 5pF RC
00302-044
2k 2k OUTPUT
SATURATION RECOVERY TIME
The OP467 has a fast and symmetrical recovery time from either rail. This feature is very useful in applications such as high speed instrumentation and measurement circuits, where the amplifier is frequently exposed to large signals that overload the amplifier.
200 10T
Figure 44. A High Speed Instrumentation Amplifier
Rev. F | Page 14 of 20
00302-043
00302-042
OP467
0.01% 10V STEP VS = 15V NEG SLOPE
2 MHz BIQUAD BAND-PASS FILTER
The circuit in Figure 48 is commonly used in medical imaging ultrasound receivers. The 30 MHz bandwidth is sufficient to accurately produce the 2 MHz center frequency, as the measured response shows in Figure 49. When the bandwidth of the op amp is too close to the center frequency of the filter, the internal phase shift of the amplifier causes excess phase shift at 2 MHz, which alters the response of the filter. In fact, if the chosen op amp has a bandwidth close to 2 MHz, the combined phase shift of the three op amps causes the loop to oscillate.
00302-045
2.5mV -2.5mV
Figure 45. Instrumentation Amplifier Settling Time to 0.01% for a 10 V Step Input (Negative Slope)
0.01% 10V STEP VS = 15V POS SLOPE
Careful consideration must be given to the layout of this circuit as with any other high speed circuit. If the phase shift introduced by the layout is large enough, it can alter the circuit performance, or worse, cause oscillation.
R6 1k C1 50pF R2 2k R1 3k 1/4 OP467 1/4 OP467 VOUT VIN R3 2k 1/4 OP467
2.5mV -2.5mV
R4 2k
C2 50pF R5 2k 1/4 OP467
00302-048
2k
Figure 46. Instrumentation Amplifier Settling Time to 0.01% for a 10 V Step Input (Positive Slope)
+VS + TO INPUT 2k +
00302-046
Figure 48. 2 MHz Biquad Filter
0
AD9617
TO IN-AMP OUTPUT 2k
1k
ERROR TO SCOPE
GAIN (dB)
-10
-20
-VS 61.9
00302-047
549
-30
Figure 47. Settling Time Measurement Circuit
-40
10k
100k
1M FREQUENCY (Hz)
10M
100M
Figure 49. Biquad Filter Response
Rev. F | Page 15 of 20
00302-049
OP467
+5V +10V
1 2
VDD VREF A RFBA IOUT 1A
DAC8408
DGND 28 VREF C 27 RFBC 26 IOUT 1C 25 IOUT 2C/ IOUT 2D 24 IOUT 1D 23 RFBD 22 VREF D 21 DS2 20 DS1 19 R/W 18 A/B 17
+10V
C1 10pF
2
3 4 5 6 7
C3 10pF
13
OUT A
1
OP467
3
IOUT 2A/ IOUT 2B IOUT 1B RFBB VREF B DB0 (LSB)
OP467
12
14
OUT D
+15V 0.1F
4 6
9
8 C2 10pF
+10V
OUT B
7
OP467
11 5
9
+10V
C4 10pF
OP467
10
8
OUT C
0.1F -15V
10 DB1 11 DB2 12 DB3 13 DB4 14 DB5
DIGITAL CONTROL SIGNALS
(MSB) DB7 16 DB6 15
00302-050
Figure 50. Quad DAC Unipolar Operation
FAST I-TO-V CONVERTER
The fast slew rate and fast settling time of the OP467 are well suited to the fast buffers and I-to-V converters used in a variety of applications. The circuit in Figure 50 is a unipolar quad DAC consisting of only two ICs. The current output of the DAC8408 is converted to a voltage by the OP467 configured as an I-to-V converter. This circuit is capable of settling to 0.1% within 200 ns. Figure 51 and Figure 52 show the full-scale settling time of the outputs. To obtain reliable circuit performance, keep the traces from the IOUT of the DAC to the inverting inputs of the OP467 short to minimize parasitic capacitance.
260.0ns
100 90 100 90
251.0ns
10 0%
2V
50mV
100ns
Figure 52. Rising Edge Output Settling Time
DAC8408 RFB 3pF IOUT I-V OP467 2k AD847 604 1k 50k 2k DC OFFSET
00302-052
10 0%
00302-051
60.4k
2V
50mV
100ns
Figure 53. DAC VOUT Settling Time Circuit
Figure 51. Falling Edge Output Settling Time
Rev. F | Page 16 of 20
00302-053
OP467
OP467 SPICE MARCO-MODEL
* Node assignments noninverting input inverting input positive supply negative supply output * . SUBCKT OP467 1 2 99 50 27 * * INPUT STAGE * I1 4 10E-3 5 0 CIN 1 2 1E-12 IOS 1 2 5E-9 Q1 5 2 8 QN Q2 6 7 9 QN R3 99 5 185 . 681 R4 99 6 185 . 681 R5 8 4 180 . 508 R6 9 4 180 . 508 EOS 7 1 POLY (1) (14,20) 50E-6 EREF 98 0 (20,0) 1 * * GAIN STAGE AND DOMINANT POLE AT 1.5 kHz * R7 10 98 3 . 714E6 C2 10 98 28 . 571E-12 G1 98 10 (5,6) 5 . 386E-3 V1 99 11 1.6 V2 12 50 1.6 D1 10 11 DX D2 12 10 DX RC 10 28 1 . 4E3 CC 28 27 12E-12 * * COMMON-MODE STAGE WITH ZERO AT 1.26 kHz * ECM 13 98 POLY (2) (1, 20) (2,20) 0 0. 5 0 . 5 R8 13 14 1E6 R9 14 98 25 . 119 C3 13 14 126 . 721E-12 * *POLE AT 400E6 * R10 15 98 1E6 C4 15 98 0 . 398E-15 G2 98 15 (10,20) 1E-6 * * OUTPUT STAGE * ISY 99 50 -8 . 183E-3 RMP1 99 20 96 . 429E3 RMP2 20 50 96 . 429E3 RO1 99 26 200 RO2 26 50 200 L1 26 27 1E-7 GO1 26 99 (99,15) 5E-3 GO2 50 26 (15,50) 5E-3 G4 23 50 (15,26) 5E-3 G5 24 50 (26,15) 5E-3 V3 21 26 50 V4 26 22 50 D3 15 21 DX D4 22 15 DX D5 99 23 DX D6 99 24 DX D7 50 23 DY D8 50 24 DY * * MODELS USED * . MODEL QN NPN (BF=33.333E3) . MODEL DX D . MODEL DY D (BV=50) . ENDS OP467
1
Rev. F | Page 17 of 20
OP467
99
99 RMP1 D5 21 D6 G01 R01 L1 26 22 24 D7 D8 G5 G02
00302-054
99 + V1 - 11 D1 7 10 C3 R7 C2 13 ECM + - D2 12 50
00302-055
99
ISY 20
R3 5
27
R4 6
V3 +-
RC
28
CC
27
15 R10 G2 EREF + - C4
D3 15 D4 RMP2 23
N-
2 IOS CIN
Q1 8 R5 -+ EOS 4
Q2 9 R6
V4 -+ R02
G1
R8
14 R9
98
1 N+
G4
EREF I1
+ -
98 V2 + -
50
50
50
Figure 54. SPICE Macro-Model Output Stage
Figure 55. SPICE Macro-Model Input and Gain Stage
Rev. F | Page 18 of 20
OP467 OUTLINE DIMENSIONS
0.775 (19.69) 0.750 (19.05) 0.735 (18.67)
14 1 8
7
0.280 (7.11) 0.250 (6.35) 0.240 (6.10) 0.325 (8.26) 0.310 (7.87) 0.300 (7.62) 0.060 (1.52) MAX 0.015 (0.38) MIN SEATING PLANE 0.005 (0.13) MIN 0.015 (0.38) GAUGE PLANE 0.430 (10.92) MAX 0.195 (4.95) 0.130 (3.30) 0.115 (2.92)
0.100 (2.54) BSC 0.210 (5.33) MAX 0.150 (3.81) 0.130 (3.30) 0.110 (2.79) 0.022 (0.56) 0.018 (0.46) 0.014 (0.36)
0.014 (0.36) 0.010 (0.25) 0.008 (0.20)
0.070 (1.78) 0.050 (1.27) 0.045 (1.14)
COMPLIANT TO JEDEC STANDARDS MS-001 CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.
Figure 56. 14-Lead Plastic Dual In-Line Package [PDIP] (N-14) P-Suffix Dimensions shown in inches and (millimeters)
0.005 (0.13) MIN
14 1
0.098 (2.49) MAX
8
7
0.310 (7.87) 0.220 (5.59)
PIN 1
0.100 (2.54) BSC 0.785 (19.94) MAX 0.060 (1.52) 0.015 (0.38)
0.320 (8.13) 0.290 (7.37)
0.200 (5.08) MAX 0.200 (5.08) 0.125 (3.18) 0.023 (0.58) 0.014 (0.36)
0.150 (3.81) MIN SEATING 0.070 (1.78) PLANE 0.030 (0.76)
15 0
0.015 (0.38) 0.008 (0.20)
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 57. 14-Lead Ceramic Dual In-Line Package [CERDIP] (Q-14) Y-Suffix Dimensions shown in inches and (millimeters)
Rev. F | Page 19 of 20
070606-A
OP467
10.50 (0.4134) 10.10 (0.3976)
16
9
7.60 (0.2992) 7.40 (0.2913)
1 8
10.65 (0.4193) 10.00 (0.3937)
1.27 (0.0500) BSC 0.30 (0.0118) 0.10 (0.0039) COPLANARITY 0.10 0.51 (0.0201) 0.31 (0.0122)
2.65 (0.1043) 2.35 (0.0925)
0.75 (0.0295) 0.25 (0.0098)
8 0 0.33 (0.0130) 0.20 (0.0079)
45
SEATING PLANE
1.27 (0.0500) 0.40 (0.0157)
COMPLIANT TO JEDEC STANDARDS MS-013- AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 58. 16-Lead Standard Small Outline Package [SOIC_W] Wide Body (RW-16) S-Suffix Dimensions shown in millimeters and (inches)
0.100 (2.54) 0.064 (1.63)
0.075 (1.91) REF 0.095 (2.41) 0.075 (1.90)
19 18
3 20 1 4
0.200 (5.08) REF 0.100 (2.54) REF 0.015 (0.38) MIN 0.028 (0.71) 0.022 (0.56) 0.050 (1.27) BSC
0.358 (9.09) 0.342 (8.69) SQ
0.358 (9.09) MAX SQ
0.011 (0.28) 0.007 (0.18) R TYP 0.075 (1.91) REF 0.055 (1.40) 0.045 (1.14)
BOTTOM VIEW
14 13 8 9
0.088 (2.24) 0.054 (1.37)
45 TYP 0.150 (3.81) BSC
022106-A
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 59. 20-Terminal Ceramic Leadless Chip Carrier [LCC] (E-20-1) RC-Suffix Dimensions shown in inches and (millimeters)
ORDERING GUIDE
Model OP467GP OP467GPZ 1 OP467GS OP467GS-REEL OP467GSZ1 OP467GSZ-REEL1 OP467ARC/883C OP467AY/883C OP467GBC
1
Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -55C to +125C -55C to +125C
Package Description 14-Lead PDIP 14-Lead PDIP 16-Lead SOIC_W 16-Lead SOIC_W 16-Lead SOIC_W 16-Lead SOIC_W 20-Terminal LCC 14-Lead CERDIP DIE
Package Option N-14 N-14 RW-16 RW-16 RW-16 RW-16 E-20-1 Q-14
Z = RoHS Compliant Part.
(c)2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C00302-0-5/07(F)
Rev. F | Page 20 of 20
032707-B

▲Up To Search▲

Price & Availability of OP46707

	To Download OP46707 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .